Search for: All records

Photonic curing is a large‐area, high‐throughput thermal processing technique that uses high‐intensity pulsed light to selectively cure thin films on thermally sensitive substrates. This study employs 3‐dimensional (3D) simulation to show, for the first time, that gate geometry significantly impacts peak curing temperature during photonic curing. The simulation results are experimentally validated by photonically curing solution‐processed indium zinc oxide for thin‐film transistors with different bottom gate geometries and comparing their performance to thermally annealed control devices. Under the same photonic curing pulse, for a fixed aspect ratio, peak photonic curing temperature increases with larger gate area, while for a fixed area, peak photonic curing temperature decreases with increasing aspect ratio. For different gate areas and aspect ratios, the simulated peak photonic curing temperature varies from ≈200 to 450 °C, which strongly impacts metal‐hydroxide to metal‐oxide conversion in sol–gels. Thus, the subsequent transistor performance is strongly influenced by the gate geometry. For example, for increasing gate area with fixed aspect ratio of 1, the average mobility increases from 1.61 to 12.52 cm² V⁻¹s⁻¹, while the threshold voltage decreases from 2.14 to −5.68 V. Thus, this study provides valuable insights for adopting 3D simulation to design transistors for complex large‐area electronics using photonic curing. 

In recent years, the increasing threat of devastating wildfires has underscored the need for effective prescribed fire management. Process-based computer simulations have traditionally been employed to plan prescribed fires for wildfire prevention. However, even simplified process models are too compute-intensive to be used for real-time decision-making. Traditional ML methods used for fire modeling offer computational speedup but struggle with physically inconsistent predictions, biased predictions due to class imbalance, biased estimates for fire spread metrics (e.g., burned area, rate of spread), and limited generalizability in out-of-distribution wind conditions. This paper introduces a novel machine learning (ML) framework that enables rapid emulation of prescribed fires while addressing these concerns. To overcome these challenges, the framework incorporates domain knowledge in the form of physical constraints, a hierarchical modeling structure to capture the interdependence among variables of interest, and also leverages pre-existing source domain data to augment training data and learn the spread of fire more effectively. Notably, improvement in fire metric (e.g., burned area) estimates offered by our framework makes it useful for fire managers, who often rely on these estimates to make decisions about prescribed burn management. Furthermore, our framework exhibits better generalization capabilities than the other ML-based fire modeling methods across diverse wind conditions and ignition patterns. 

Abstract In metal‐oxide thin‐film transistors (TFTs), high‐kgate dielectrics often yield a higher electron mobility than SiO₂. However, investigations regarding the mechanism of this high‐k“mobility boost” are relatively scarce. To explore this phenomenon, solution‐processed In₂O₃TFTs are fabricated using eight different gate dielectrics (SiO₂, Al₂O₃, ZrO₂, HfO₂, and bilayer SiO₂/high‐kstructures). With these structures, the total gate capacitance can be varied independently from the semiconductor–dielectric interface to study this mobility enhancement. It is shown that the mobility enhancement is a combination of the effects of areal gate capacitance and interface quality for disordered oxide semiconductor devices. The ZrO₂‐gated TFTs achieve the highest mobility by inducing more accumulation charge with higher gate capacitance. Surprisingly, however, when the gate capacitance is held constant, no mobility enhancement is observed with the high‐kgate dielectrics compared to SiO₂.